1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device, and more particularly, to a method of designing an ASIC type semiconductor integrated circuit device.
2. Description of the Related Art
A serial interface is a system for transferring data between LSIs at high speed with a reduced number of cables. For example, as shown in FIG. 1, the serial interface is mounted on an LSI to interconnect functional blocks such as a PLL (Phase Locked Loop) circuit 1, a transmitting section 2, and a receiving section 3.
The PLL circuit 1 inputs a differential clock signal 1a of 125 MHz which is supplied from outside the LSI and increases the differential clock signal 1a to 10 times in frequency to output the 1.25-GHz clock signal 4. At the same time, the PLL circuit 1 outputs the 125-MHz clock signal 5. These clock signals 4 and 5 are supplied to the transmitting section 2 and the receiving section 3 through clock buffers 6. The receiving section 3 inputs a differential serial data signal 3a of 1.25 Gbps and outputs a 10-bit parallel data signal of 125 Mbps. Also, the transmitting section 2 inputs the 10-bit parallel data signal 3c of 125 Mbps and outputs a differential serial data signal 3d of 1.25 Gbps.
Next, the operation of the transmitting section and receiving section will be described below in detail.
First, the structure and operation of the transmitting section 2 will be described.
Referring to FIG. 2, the transmitting section 2 is composed of a 10:1 MUX circuit. The transmitting section 2 is provided with a register 7 composed of flip-flop (F/F) circuits 9, and a shift register 8 composed of flip-flop circuits 10 and selectors 11.
In the transmitting section 2, data 0 to data 9 of 10-bit parallel data 3c are taken in by the register 7 in response to a clock signal 5 of 125 MHz. After that, the data 0 to the data 9 are transferred from the register 7 to the shift register 8 based on the clock signal 4 of 1.25 GHz and a selection signal 8a. In this way, a serial data sequence 3d of 10 bits is obtained.
Next, the structure and operation of receiving section 3 will be described.
As shown in FIG. 3, the receiving section 3 is composed of a 1:10 demultiplexing (DEMUX) circuit with a clock recovery circuit block 12 added. The clock recovery circuit block 12 monitors the switching edge of the received data signal 3a of 1.25 Gbps to generate the 1.25-GHz clock signal with an optimal phase. Thus, the retiming of the received data is carried out. At this time, generally, the clock signal 4 of 1.25 GHz generated by the above mentioned PLL circuit 1 is supplied to the clock recovery circuit block 12 as a reference signal.
In the demultiplexing circuit, the 1.25 Gbps serial data 3a is taken in the shift register 14 in response to a clock signal 13, and then is taken in a register 16 in response to a 125-MHz clock signal 15. Then, the serial data is outputted as the parallel data 3b of 125 Mbps. A frequency divider 14a divides the 1.25-GHz clock signal 13 in frequency to {fraction (1/10)} to generate the 125-MHz clock signal 15. The reference numerals 17 and 18 are flip-flop circuits of the shift register 14 and register 16, respectively.
The serial interface for one channel is realized for the above mentioned PLL circuit 1, transmitting section 2, and the receiving section 3 to handle transmission data and reception data. However, actually, the serial interfaces for a plurality of channels are often provided for a single LSI.
As shown in FIG. 4, in order to realize this, the circuits such as the PLL circuit 1 are generally common to receiving section/transmitting sections (transmitting section 2 and receiving section 3) for all channels 101. Because the receiving section/transmitting section 101 must be reliably operated for all the channels, the input condition of the clock signals 4 and 5 to the receiving section/transmitting section 101 for the respective channels must be uniformly kept. Therefore, in such a structure, the distribution of the clock signals 4 and 5 from PLL circuit 1 to the receiving section/transmitting sections 101 is important. For this purpose, it is necessary to use a carefully designed clock tree 102.
The clock tree 102 is formed by connecting buffers 6 of a plurality of stages. In this case, wiring line lengths between the stages are made equal to each other, and the structures of paths of the clock tree are made equal to each other so that a clock skew can be reduced.
Therefore, in a conventional ASIC (Application Specific Integrated Circuit) which includes a serial interface circuit, as shown in FIG. 4, the receiving section/transmitting sections 101 and the PLL circuit 1 are described in an ASIC design data base as independent macros. The clock tree 102 is designed specifically for every kind of macro, to connect between them. Also, a wiring line structure for the exclusive use is designed for every kind of macro in case that the circuit which needs a power supply circuit is used for the receiving section/transmitting sections. Also, the wiring line structure for the exclusive use is designed in case that a signal is communicated from the receiving section/transmitting sections to a common section.
When the serial data interface circuit is mounted on the conventional ASIC system semiconductor integrated circuit device as mentioned above, it is necessary to carefully design the semiconductor integrated circuit device for every kind of macro, resulting in a long design turn-around time, and lack in the uniformity of the design quality.
An integrated circuit device is described in Japanese Laid Open Patent Application (JP-A-Showa 60-1845: first conventional example). In this reference, the occupation area of a single chip for a circuit layout pattern having a function has an overlapping shape through a symmetrical conversion.
A method of forming a master slice type integrated circuit device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-24763: second conventional example). In this reference, a wiring line layout pattern to a pair of function blocks is formed in a point symmetry or in a mirror symmetry. Each of the function blocks is composed of at least one basic cell and the function blocks have the same circuit structure. According to the conventional example, the input/output pin positions of each of the logical function blocks can be arranged in symmetrical positions. Also, the unevenness of the wiring line length which is caused by the position relation of the input/output pins is eliminated. Moreover, when it is requested that the wiring line lengths between the respective logical function blocks are made equal to each other for the parallel processing of a plurality of signals, the influence of the input/output pin position of each logical function block is removed. The unevenness of the wiring line length which is caused by the position relation of the input/output pins is eliminated.
In Japanese Laid Open Patent Application (JP-A-Heisei 4-372169: a third conventional example), a master slice LSI can be obtained. In this reference, a macro cell is composed of terminals which are in the same positions, the same number of basic cells, and a delay element provided between the input terminal and the output terminal on a signal propagation route and having one of a plurality of delay values. Therefore, one macro cell can be easily replaced by another macro cell having the desired delay value. Also, it is not necessary to insert a new delay element once again by carrying out the design again. In addition, a timing error, can be easily eliminated.
In Japanese Laid Open Patent Application (JP-A-Heisei 5-29459: a fourth conventional example), it is described that when a semiconductor substrate area is divided into a plurality of regions for a process of forming wiring lines, wiring line peripheral regions which separate the wiring line regions are set such that a sequence of input/output pins of a hard macro is made parallel, and a connection terminal is provided at the intersection with a perpendicular line from the input/output pin of the hard macro to the wiring line peripheral region.
In Japanese Laid Open Patent Application (JP-A-Heisei 1-283950: a fifth conventional example), a following semiconductor integrated circuit device is described. That is, the layout pattern of an LSI output buffer cell with a scan pass, a shift-in terminal is provided onto the first side of the output buffer cell. A shift-out terminal is provided onto the second side which faces the first side. Terminals other than the above mentioned terminals are arranged on the third side other than the first and second sides to connect with the inside of the LSI chip. The first and second terminals for the feed-through are provided on the second side which faces the first side in the input buffer cell to be connected with each other in the inside the input buffer cell. The positions of the shift-in terminal, shift-out terminal of the above output buffer cell, and the first and second terminals in the input buffer cell are arranged. In this way, when a plurality of output buffer cells are arranged adjacently in a direction, or when a plurality of output buffer cells and a plurality of input buffer cells are arranged adjacently in a direction, the shift-in terminal and the shift-out terminal of each output buffer cell are automatically connected directly or through feed-through terminals in the input buffer cell.
The object of the above fifth conventional example is the deletion of a wiring line area. Therefore, in an output buffer containing a scan pass, a shift-in terminal and a shift-out terminal are arranged on the coordinate with the same height in the sides of the buffer block. Therefore, in the above fifth conventional example, the scan wiring line is connected in the side of the output buffer without passing through the internal area to link the respective output buffers in the order. Therefore, the internal automatic wiring line area can be saved.
However, there is no description on the structure of each block in the above fifth conventional example. The application field is a scan pass structure and the critical timing does not exist. Therefore, a device is not needed in the structure in each block. Even if the above fifth conventional example is applied to the same field as the present invention, the above fifth conventional example does not guarantee the critical timing.
Therefore, an object of the present invention is to provide a method of designing a semiconductor integrated circuit device simply and surely, and a semiconductor integrated circuit device manufactured by the same.
Another object of the present invention is to provide a method of designing a semiconductor integrated circuit device with a multi-channel serial interface circuit to provide stable characteristics and a semiconductor integrated circuit device manufactured by the same.
Still another object of the present invention is to provide a method of designing a semiconductor integrated circuit device by use of less libraries, and a semiconductor integrated circuit device manufactured by the same.
Yet still another object of the present invention is to provide a method of designing a semiconductor integrated circuit device by providing layout patterns for terminals at corresponding positions, and a semiconductor integrated circuit device manufactured by the same.
It is also an object of the present invention to provide a recording medium storing a program for either of the above methods.
In order to achieve an aspect of the present invention, a method of designing a semiconductor integrated circuit device is carried out by providing a common block macro for a common circuit and data communication block macros, and arranging the common block macro and the data communication block macros to form a layout pattern of a semiconductor integrated circuit device. Each of the data communication block macros is for a data communication circuit. Each of the data communication block macros has a layout pattern for an input terminal for a signal and a layout pattern for an output terminal for the signal at corresponding positions between the data communication block macros. Also, the common block macro has a layout pattern for an output terminal for the signal at a position corresponding to the layout pattern for the input terminal of the data communication block macro.
Here, the signal may be a clock signal. In this case, the common block macro desirably includes a layout pattern for a clock driver. Also, the common block macro may include a layout pattern for a PLL (Phase Locked Loop) circuit.
Also, the signal may be a reference voltage signal indicative of a reference voltage. In this case, the common block macro may include a layout pattern for a reference voltage generating circuit which generates the reference voltage.
Also, each of the data communication block macros may have a first layout pattern for the data communication circuit, and a second layout pattern for a transfer section for the signal. At this time, the transfer section may include a first wiring line connected to the input terminal, and a first buffer connected between the first wiring line and the output terminal. The transfer section may further include a second wiring line connected to the first wiring line, and a buffering section having at least one second buffer and provided between the data communication circuit and the second wiring line. In this case, the arranging of the data communication block macros is carried out based on the number of second buffers. It is desirable that a summation of the number of the first buffers and the number of the secondxcx9cbuffers from the common circuit to the data communication circuit in each of the data communication block macros is the same between the data communication block macros. In addition, it is desirable that a summation of the first and second wiring lines in length from the common circuit to the data communication circuit in each of the data communication block macros is the same between the data communication block macros. The buffering section may include a plurality of the second buffers, and each of the plurality of second buffers is connected with a capacitor corresponding to the first buffer other than one second buffer.
In order to achieve another aspect of the present invention, a method of designing a semiconductor integrated circuit device is carried out by providing a common block macro for a common circuit, a data communication circuit macro for a data communication circuit, and transfer section macros for transfer sections, by arranging the common block macro in an area, and by arranging sets of the data communication circuit macro and one of the transfer section macros in other areas, respectively, to form a layout pattern of a semiconductor integrated circuit device. Each of the transfer section macros has a layout pattern for an input terminal of a signal and a layout pattern for an output terminal of the signal at corresponding positions between the transfer section macros. The common block macro has a layout pattern for an output terminal of the signal at a position corresponding to the layout pattern for the input terminal of the transfer section macro.
Here, the signal may be a clock signal. In this case, the common block macro desirably includes a layout pattern for a clock driver. Also, the common block macro desirably includes a layout pattern for a PLL (Phase Locked Loop) circuit.
Also, the signal may be a reference voltage signal indicative of a reference voltage. In this case, the common block macro may include a layout pattern for a reference voltage generating circuit which generates the reference voltage.
Also, the transfer section may include a first wiring line connected to the input terminal, a first buffer connected between the first wiring line and the output terminal, a second wiring line connected to the first wiring line, and a buffering section having at least one second buffer and provided between the communication circuit and the second wiring line. In this case, the arranging of the sets of the data communication circuit macro and the one transfer section macro is carried out based on the number of the second buffers. At this time, it is desirable that a summation of the number of the first buffers and the number of the second buffers from the common circuit to the data communication circuit is the same between the sets of the data communication circuit macro and the one transfer section macro. In addition, it is desirable that a summation of the first and second wiring lines in length from the common circuit to the data communication circuit is the same between the sets of the data communication circuit macro and the one transfer section macro.
Also, when the buffering section includes a plurality of the second buffers, each of the second buffers may be connected with a capacitor corresponding to the first buffer other than one second buffer.
In order to achieve still another aspect of the present invention, there is provided a recording medium storing a program for a method of designing a semiconductor integrated circuit device. At this time, a method of designing a semiconductor integrated circuit device is carried out by providing a common block macro for a common circuit and data communication block macros, and arranging the common block macro and the data communication block macros to form a layout pattern of a semiconductor integrated circuit device. Each of the data communication block macros is for a data communication circuit. Each of the data communication block macros has a layout pattern for an input terminal for a signal and a layout pattern for an output terminal for the signal at corresponding positions between the data communication block macros. Also, the common block macro has a layout pattern for an output terminal for the signal at a position corresponding to the layout pattern for the input terminal of the data communication block macro.
Here, the signal may be a clock signal. In this case, the common block macro desirably includes a layout pattern for a clock driver. Also, the common block macro may include a layout pattern for a PLL (Phase Locked Loop) circuit.
Also, the signal may be a reference voltage signal indicative of a reference voltage. In this case, the common block macro may include a layout pattern for a reference voltage generating circuit which generates the reference voltage.
Also, each of the data communication block macros may have a first layout pattern for the data communication circuit, and a second layout pattern for a transfer section for the signal. At this time, the transfer section may include a first wiring line connected to the input terminal, and a first buffer connected between the first wiring line and the output terminal. The transfer section may further include a second wiring line connected to the first wiring line, and a buffering section having at least one second buffer and provided between the data communication circuit and the second wiring line. In this case, the arranging of the data communication block macros is carried out based on the number of second buffers. It is desirable that a summation of the number of the first buffers and the number of the second buffers from the common circuit to the data communication circuit in each of the data communication block macros is the same between the data communication block macros. In addition, it is desirable that a summation of the first and second wiring lines in length from the common circuit to the data communication circuit in each of the data communication block macros is the same between the data communication block macros. The buffering section may include a plurality of the second buffers, and each of the plurality of second buffers is connected with a capacitor corresponding to the first buffer other than one second buffer.
In order to achieve yet still another aspect of the present invention, a method of designing a semiconductor integrated circuit device is carried out by providing a common block macro for a common circuit, a data communication circuit macro for a data communication circuit, and transfer section macros for transfer sections, by arranging the common block macro in an area, and by arranging sets of the data communication circuit macro and one of the transfer section macros in other areas, respectively, to form a layout pattern of a semiconductor integrated circuit device. Each of the transfer section macros has a layout pattern for an input terminal of a signal and a layout pattern for an output terminal of the signal at corresponding positions between the transfer section macros. The common block macro has a layout pattern for an output terminal of the signal at a position corresponding to the layout pattern for the input terminal of the transfer section macro.
Here, the signal may be a clock signal. In this case, the common block macro desirably includes a layout pattern for a clock driver. Also, the common block macro desirably includes a layout pattern for a PLL (Phase Locked Loop) circuit.
Also, the signal may be a reference voltage signal indicative of a reference voltage. In this case, the common block macro may include a layout pattern for a reference voltage generating circuit which generates the reference voltage.
Also, the transfer section may includes a first wiring line connected to the input terminal, a first buffer connected between the first wiring line and the output terminal, a second wiring line connected to the first wiring line, and a buffering section having at least one second buffer and provided between the communication circuit and the second wiring line. In this case, the arranging of the sets of the data communication circuit macro and the one transfer section macro is carried out based on the number of the second buffers. At this time, it is desirable that a summation of the number of the first buffers and the number of the second buffers from the common circuit to the data communication circuit is the same between the sets of the data communication circuit macro and the one transfer section macro. In addition, it is desirable that a summation of the first and second wiring lines in length from the common circuit to the data communication circuit is the same between the sets of the data communication circuit macro and the one transfer section macro.
Also, when the buffering section includes a plurality of the second buffers, each of the second buffers may be connected with a capacitor corresponding to the first buffer other than one second buffer.